//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : 
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths


module AUPP_FIFO(
   input                      GTM_AUPP_RESET,
   input                      GTM_RX_CKOCK,
   input                      GTM_SYS_CKOCK,
   // input write data from point analysis module.
   input[2:0]                 FFWR_IN_CHNN,
   input[7:0]                 FFWR_IN_WADDR,
   input                      FFWR_IN_WE,
   input[7:0]                 FFWR_IN_DATA,
   input                      FFWR_IN_J1,
   input                      FFWR_IN_AIS,

   //
   input[2:0]                 FFRD_IN_CHNN,
   input[7:0]                 FFRD_IN_RADDR,
   output[7:0]                FFRD_OUT_DATA,
   output                     FFRD_OUT_J1,
   output                     FFRD_OUT_AIS,
   output[5:0]                FFRD_OUT_FIFO_BGWADDR
   );


//
wire                          DATA_FIFO_RAM_CLKA, DATA_FIFO_RAM_CLKB;
wire                          DATA_FIFO_RAM_WEA;
wire[10:0]                    DATA_FIFO_RAM_ADDRA, DATA_FIFO_RAM_ADDRB;
wire[8:0]                     DATA_FIFO_RAM_DINA, DATA_FIFO_RAM_DOUTB;


wire[2:0]                     WRSYNC_FFWR_CHNN;
wire                          WRSYNC_FFWR_AIS;
wire                          WRSYNC_FFWR_EN;
wire[7:0]                     WRSYNC_FFWR_ADDR;

wire                          WA_RAM_CLKA, WA_RAM_CLKB;
wire                          WA_RAM_WEA;
wire[2:0]                     WA_RAM_ADDRA, WA_RAM_ADDRB;
wire[8:0]                     WA_RAM_RAM_DINA, WA_RAM_DOUTB;


// ++++++++++++++++++ Section 3: Data FIFO and FIFO write address transfer   ++++++++++++++++++ //
  assign DATA_FIFO_RAM_CLKA                = GTM_RX_CKOCK;
  assign DATA_FIFO_RAM_WEA                 = FFWR_IN_WE;
  assign DATA_FIFO_RAM_ADDRA[10:0]         = { FFWR_IN_CHNN[2:0], FFWR_IN_WADDR[7:0] };
  assign DATA_FIFO_RAM_DINA[7:0]           = FFWR_IN_DATA[7:0];
  assign DATA_FIFO_RAM_DINA[8]             = FFWR_IN_J1;            
  
  assign DATA_FIFO_RAM_CLKB                = GTM_SYS_CKOCK;
  assign DATA_FIFO_RAM_ADDRB[10:0]         = { FFRD_IN_CHNN[2:0], FFRD_IN_RADDR[7:0] };
  assign FFRD_OUT_DATA[7:0]                = DATA_FIFO_RAM_DOUTB[7:0];
  assign FFRD_OUT_J1                       = DATA_FIFO_RAM_DOUTB[8];

AURG_FIFO_RAM18K_9_9                       INST_DATA_FIFO_RAM18K_9_9(
   .CLKA                                   ( DATA_FIFO_RAM_CLKA ),
   .WEA                                    ( DATA_FIFO_RAM_WEA ),
   .ADDRA                                  ( DATA_FIFO_RAM_ADDRA[10:0] ),
   .DINA                                   ( DATA_FIFO_RAM_DINA ),

   .CLKB                                   ( DATA_FIFO_RAM_CLKB ),
   .ADDRB                                  ( DATA_FIFO_RAM_ADDRB[10:0] ),
   .DOUTB                                  ( DATA_FIFO_RAM_DOUTB[8:0] )
   );


AUPP_WRSYNC                                INST_AUPP_WRSYNC(
   .GTM_AUPP_RESET                         ( GTM_AUPP_RESET ),
   .GTM_RX_CKOCK                           ( GTM_RX_CKOCK ),
   .GTM_SYS_CKOCK                          ( GTM_SYS_CKOCK ),
   // input write data from point analysis module.
   .SYNC_IN_FFWR_CHNN                      ( FFWR_IN_CHNN[2:0] ),
   .SYNC_IN_FFWR_AIS                       ( FFWR_IN_AIS ),
   .SYNC_IN_FFWR_EN                        ( FFWR_IN_WE ),
   .SYNC_IN_FFWR_ADDR                      ( FFWR_IN_WADDR[7:0] ),

   .SYNC_OUT_FFWR_CHNN                     ( WRSYNC_FFWR_CHNN[2:0] ),
   .SYNC_OUT_FFWR_AIS                      ( WRSYNC_FFWR_AIS ),
   .SYNC_OUT_FFWR_EN                       ( WRSYNC_FFWR_EN ),
   .SYNC_OUT_FFWR_ADDR                     ( WRSYNC_FFWR_ADDR[7:0] )
   );

  assign WA_RAM_CLKA                       = GTM_SYS_CKOCK;
  assign WA_RAM_WEA                        = WRSYNC_FFWR_EN;
  assign WA_RAM_ADDRA[2:0]                 = WRSYNC_FFWR_CHNN[2:0];
  assign WA_RAM_RAM_DINA[7:0]              = WRSYNC_FFWR_ADDR[7:0];
  assign WA_RAM_RAM_DINA[8]                = WRSYNC_FFWR_AIS;

  assign  WA_RAM_CLKB                      = GTM_SYS_CKOCK;
  assign  WA_RAM_ADDRB[2:0]                = FFRD_IN_CHNN[2:0];
  assign  FFRD_OUT_FIFO_BGWADDR[5:0]       = WA_RAM_DOUTB[5:0];
  assign  FFRD_OUT_AIS                     = WA_RAM_DOUTB[8];

AURG_FIFO_RAM72_9_9                        INST_WA_RAM72_9_9(
   .CLKA                                   ( WA_RAM_CLKA ),
   .WEA                                    ( WA_RAM_WEA ),
   .ADDRA                                  ( WA_RAM_ADDRA[2:0] ),
   .DINA                                   ( WA_RAM_RAM_DINA[8:0] ),

   .CLKB                                   ( WA_RAM_CLKB ),
   .ADDRB                                  ( WA_RAM_ADDRB[2:0] ),
   .DOUTB                                  ( WA_RAM_DOUTB[8:0] )
   );

endmodule
